On 01/04/2018 01:33 PM, Linus Torvalds wrote: > On Thu, Jan 4, 2018 at 3:26 AM, Pavel Machek <pa...@ucw.cz> wrote: >> On Wed 2018-01-03 15:51:35, Linus Torvalds wrote: >>> >>> A *competent* CPU engineer would fix this by making sure speculation >>> doesn't happen across protection domains. Maybe even a L1 I$ that is >>> keyed by CPL. >> >> Would that be enough? > > No, you'd need to add the CPL to the branch target buffer itself, not the I$ > L1. > > And as somebody pointed out, that only helps the user space messing > with the kernel. It doesn't help the "one user context fools another > user context to mispredict". (Where the user contexts might be a > JIT'ed JS vs the rest of the web browser). > > So you really would want to just make sure the full address is used to > index (or at least verify) the BTB lookup, and even then you'd then > need to invalidate the BTB on context switches so that one context > can't fill in data for another context.
IMO the correct hardware fix is to index the BTB using the full VA including the ASID/PCID. And guarantee (as is the case) that there is not a live conflict between address space identifiers with entries. The sad thing is that even the latest academic courses recommend "optimizing" branch predictors with a few low order bits (e.g. 31 in Intel's case, various others for different vendors). The fix for variant 3 is similarly not that difficult in new hardware: don't allow the speculated load to happen by enforcing the permission check at the right time. The last several editions of Computer Architecture spell this out in Appendix B (page 37 or thereabouts). Jon. -- Computer Architect | Sent from my Fedora powered laptop