From: Thomas Gleixner <[email protected]> XX: I am utterly unconvinced that having "friendly, self-explanatory" names for the IBRS-frobbing inlines is useful. There be dragons here for anyone who isn't intimately familiar with what's going on, and it's almost better to just call it IBRS, put a reference to the spec, and have a clear "you must be →this← tall to ride."
[karahmed: switch to using ALTERNATIVES instead of static_cpu_has] [dwmw2: wrmsr args inside the ALTERNATIVE again, bikeshed naming] Signed-off-by: Thomas Gleixner <[email protected]> Signed-off-by: KarimAllah Ahmed <[email protected]> Signed-off-by: David Woodhouse <[email protected]> --- arch/x86/include/asm/nospec-branch.h | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h index 8759449..5be3443 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -232,5 +232,41 @@ static inline void indirect_branch_prediction_barrier(void) : "memory"); } +/* + * This also performs a barrier, and setting it again when it was already + * set is NOT a no-op. + */ +static inline void restrict_branch_speculation(void) +{ + unsigned long ax, cx, dx; + + asm volatile(ALTERNATIVE("", + "movl %[msr], %%ecx\n\t" + "movl %[val], %%eax\n\t" + "movl $0, %%edx\n\t" + "wrmsr", + X86_FEATURE_IBRS) + : "=a" (ax), "=c" (cx), "=d" (dx) + : [msr] "i" (MSR_IA32_SPEC_CTRL), + [val] "i" (SPEC_CTRL_IBRS) + : "memory"); +} + +static inline void unrestrict_branch_speculation(void) +{ + unsigned long ax, cx, dx; + + asm volatile(ALTERNATIVE("", + "movl %[msr], %%ecx\n\t" + "movl %[val], %%eax\n\t" + "movl $0, %%edx\n\t" + "wrmsr", + X86_FEATURE_IBRS) + : "=a" (ax), "=c" (cx), "=d" (dx) + : [msr] "i" (MSR_IA32_SPEC_CTRL), + [val] "i" (0) + : "memory"); +} + #endif /* __ASSEMBLY__ */ #endif /* __NOSPEC_BRANCH_H__ */ -- 2.7.4
