* David Woodhouse <d...@amazon.co.uk> wrote:
> Add three feature bits exposed by new microcode on Intel CPUs for
> speculation control. We would now be up to five bits in CPUID(7).RDX
> so take them out of the 'scattered' features and make a proper word
> for them instead as that leaf is a pure feature bits leaf.
>
> [bp: heckle commitlog]
> Signed-off-by: David Woodhouse <d...@amazon.co.uk>
> Reviewed-by: Borislav Petkov <b...@suse.de>
> ---
> arch/x86/include/asm/cpufeature.h | 7 +++++--
> arch/x86/include/asm/cpufeatures.h | 12 +++++++++---
> arch/x86/include/asm/disabled-features.h | 3 ++-
> arch/x86/include/asm/required-features.h | 3 ++-
> arch/x86/kernel/cpu/common.c | 1 +
> arch/x86/kernel/cpu/scattered.c | 2 --
> 6 files changed, 19 insertions(+), 9 deletions(-)
>
> diff --git a/arch/x86/include/asm/cpufeature.h
> b/arch/x86/include/asm/cpufeature.h
> index ea9a7dd..70eddb3 100644
> --- a/arch/x86/include/asm/cpufeature.h
> +++ b/arch/x86/include/asm/cpufeature.h
> @@ -29,6 +29,7 @@ enum cpuid_leafs
> CPUID_8000_000A_EDX,
> CPUID_7_ECX,
> CPUID_8000_0007_EBX,
> + CPUID_7_EDX,
> };
>
> #ifdef CONFIG_X86_FEATURE_NAMES
> @@ -79,8 +80,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
> CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 15, feature_bit) || \
> CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 16, feature_bit) || \
> CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) || \
> + CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) || \
> REQUIRED_MASK_CHECK || \
> - BUILD_BUG_ON_ZERO(NCAPINTS != 18))
> + BUILD_BUG_ON_ZERO(NCAPINTS != 19))
>
> #define DISABLED_MASK_BIT_SET(feature_bit) \
> ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \
> @@ -101,8 +103,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
> CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 15, feature_bit) || \
> CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 16, feature_bit) || \
> CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) || \
> + CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) || \
> DISABLED_MASK_CHECK || \
> - BUILD_BUG_ON_ZERO(NCAPINTS != 18))
> + BUILD_BUG_ON_ZERO(NCAPINTS != 19))
>
> #define cpu_has(c, bit)
> \
> (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
> diff --git a/arch/x86/include/asm/cpufeatures.h
> b/arch/x86/include/asm/cpufeatures.h
> index 25b9375..2efb8d4 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -13,7 +13,7 @@
> /*
> * Defines x86 CPU feature bits
> */
> -#define NCAPINTS 18 /* N 32-bit words worth of
> info */
> +#define NCAPINTS 19 /* N 32-bit words worth of
> info */
> #define NBUGINTS 1 /* N 32-bit bug flags */
>
> /*
> @@ -206,8 +206,6 @@
> #define X86_FEATURE_RETPOLINE ( 7*32+12) /* Generic Retpoline
> mitigation for Spectre variant 2 */
> #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline mitigation
> for Spectre variant 2 */
> #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor
> Inventory Number */
> -#define X86_FEATURE_AVX512_4VNNIW ( 7*32+16) /* AVX-512 Neural Network
> Instructions */
> -#define X86_FEATURE_AVX512_4FMAPS ( 7*32+17) /* AVX-512 Multiply
> Accumulation Single precision */
>
> #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth
> Allocation */
> #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on
> context switches */
> @@ -319,6 +317,14 @@
> #define X86_FEATURE_SUCCOR (17*32+ 1) /* Uncorrectable error
> containment and recovery */
> #define X86_FEATURE_SMCA (17*32+ 3) /* Scalable MCA */
>
> +/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
> +#define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network
> Instructions */
> +#define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply
> Accumulation Single precision */
> +#define X86_FEATURE_SPEC_CTRL (18*32+26) /* Speculation
> Control (IBRS + IBPB) */
> +#define X86_FEATURE_STIBP (18*32+27) /* Single Thread Indirect
> Branch Predictors */
> +#define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /*
> IA32_ARCH_CAPABILITIES MSR (Intel) */
Ok, this patch should be split into at least two patches:
- one extending the feature words from 18 to 19 and moving the two vector
computing feature bits
- a separate one adding the speculation control bits
Thanks,
Ingo
