On 1/21/2018 12:01 PM, Andrew Cooper wrote:
> On 21/01/18 17:50, Tom Lendacky wrote:
>> On 1/21/2018 3:49 AM, David Woodhouse wrote:
>>> AMD doesn't implement the Speculation Control MSR that Intel does, but
>>> the Prediction Control MSR does exist and is advertised by a separate
>>> CPUID bit. Add support for that.
>>>
>>> Signed-off-by: David Woodhouse <d...@amazon.co.uk>
>>> ---
>>> arch/x86/include/asm/cpufeatures.h | 1 +
>>> arch/x86/kernel/cpu/scattered.c | 1 +
>>> 2 files changed, 2 insertions(+)
>>>
>>> diff --git a/arch/x86/include/asm/cpufeatures.h
>>> b/arch/x86/include/asm/cpufeatures.h
>>> index 2efb8d4..8c9e5c0 100644
>>> --- a/arch/x86/include/asm/cpufeatures.h
>>> +++ b/arch/x86/include/asm/cpufeatures.h
>>> @@ -207,6 +207,7 @@
>>> #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline mitigation
>>> for Spectre variant 2 */
>>> #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor
>>> Inventory Number */
>>>
>>> +#define X86_FEATURE_AMD_PRED_CMD ( 7*32+17) /* Prediction Command MSR
>>> (AMD) */
>>> #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth
>>> Allocation */
>>> #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on
>>> context switches */
>>>
>>> diff --git a/arch/x86/kernel/cpu/scattered.c
>>> b/arch/x86/kernel/cpu/scattered.c
>>> index df11f5d..4eb90b2 100644
>>> --- a/arch/x86/kernel/cpu/scattered.c
>>> +++ b/arch/x86/kernel/cpu/scattered.c
>>> @@ -28,6 +28,7 @@ static const struct cpuid_bit cpuid_bits[] = {
>>> { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 },
>>> { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },
>>> { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
>>> + { X86_FEATURE_AMD_PRED_CMD, CPUID_EBX, 12, 0x80000008, 0 },
>> I replied to the previous version, but I'll add it here, too.
>>
>> This should be moved to the existing 0x80000008/EBX entry rather than have
>> it in scattered.
>>
>> Also, there will be a total of three bits:
>> IBPB: 0x80000008 EBX[12]
>> IBRS: 0x80000008 EBX[14]
>> STIBP: 0x80000008 EBX[15]
>>
>> Since IBRS and STIBP share the same MSR, if a processor only supports
>> STIBP (MSR bit 1), for ease of software implementation the processor
>> does not GP fault attempts to write bit 0. In a similar manner, if a
>> processor only suppors IBRS (MSR bit 0), the processor does not GP
>> fault attempts to write bit 1.
>
> Are you able to comment on the read behaviour after a write which is
> ignored?
>
> If the behaviour is "read as written" then virt cases are fine. If the
> "ignore" causes a zero to be read back, then we're still going to need
> to intercept and emulate all VM accesses.
The behavior is "read as written", so the bit will be updated even though
the support for the bit is not present.
Thanks,
Tom
>
> Thanks,
>
> ~Andrew
>
