On Tue, Jan 02, 2018 at 11:31:21AM +0000, Matt Redfearn wrote: > Currently the bits to be set in the watchhi register in addition to that > requested by the user is defined inline for each register. To avoid > this, define the bits once and or that in for each register. > > Signed-off-by: Matt Redfearn <[email protected]>
Reviewed-by: James Hogan <[email protected]> Cheers James > --- > > arch/mips/kernel/watch.c | 17 +++++++---------- > 1 file changed, 7 insertions(+), 10 deletions(-) > > diff --git a/arch/mips/kernel/watch.c b/arch/mips/kernel/watch.c > index 19fcab7348b1..329d2209521d 100644 > --- a/arch/mips/kernel/watch.c > +++ b/arch/mips/kernel/watch.c > @@ -18,27 +18,24 @@ > void mips_install_watch_registers(struct task_struct *t) > { > struct mips3264_watch_reg_state *watches = &t->thread.watch.mips3264; > + unsigned int watchhi = MIPS_WATCHHI_G | /* Trap all ASIDs */ > + MIPS_WATCHHI_IRW; /* Clear result bits */ > + > switch (current_cpu_data.watch_reg_use_cnt) { > default: > BUG(); > case 4: > write_c0_watchlo3(watches->watchlo[3]); > - /* Write 1 to the I, R, and W bits to clear them, and > - 1 to G so all ASIDs are trapped. */ > - write_c0_watchhi3(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW | > - watches->watchhi[3]); > + write_c0_watchhi3(watchhi | watches->watchhi[3]); > case 3: > write_c0_watchlo2(watches->watchlo[2]); > - write_c0_watchhi2(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW | > - watches->watchhi[2]); > + write_c0_watchhi2(watchhi | watches->watchhi[2]); > case 2: > write_c0_watchlo1(watches->watchlo[1]); > - write_c0_watchhi1(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW | > - watches->watchhi[1]); > + write_c0_watchhi1(watchhi | watches->watchhi[1]); > case 1: > write_c0_watchlo0(watches->watchlo[0]); > - write_c0_watchhi0(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW | > - watches->watchhi[0]); > + write_c0_watchhi0(watchhi | watches->watchhi[0]); > } > } > > -- > 2.7.4 > >
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