On Fri, Feb 2, 2018 at 2:53 AM, Darren Kenny <[email protected]> wrote: > On Thu, Feb 01, 2018 at 10:59:44PM +0100, KarimAllah Ahmed wrote: >> >> Intel processors use MSR_IA32_ARCH_CAPABILITIES MSR to indicate RDCL_NO >> (bit 0) and IBRS_ALL (bit 1). This is a read-only MSR. By default the >> contents will come directly from the hardware, but user-space can still >> override it. >> >> [dwmw2: The bit in kvm_cpuid_7_0_edx_x86_features can be unconditional] >> >> Cc: Asit Mallick <[email protected]> >> Cc: Dave Hansen <[email protected]> >> Cc: Arjan Van De Ven <[email protected]> >> Cc: Tim Chen <[email protected]> >> Cc: Linus Torvalds <[email protected]> >> Cc: Andrea Arcangeli <[email protected]> >> Cc: Andi Kleen <[email protected]> >> Cc: Thomas Gleixner <[email protected]> >> Cc: Dan Williams <[email protected]> >> Cc: Jun Nakajima <[email protected]> >> Cc: Andy Lutomirski <[email protected]> >> Cc: Greg KH <[email protected]> >> Cc: Paolo Bonzini <[email protected]> >> Cc: Ashok Raj <[email protected]> >> Reviewed-by: Paolo Bonzini <[email protected]> >> Signed-off-by: KarimAllah Ahmed <[email protected]> >> Signed-off-by: David Woodhouse <[email protected]> > > > Reviewed-by: Darren Kenny <[email protected]>
Reviewed-by: Jim Mattson <[email protected]>
