On Tue, Feb 13, 2018 at 3:24 AM, Wu Hao <[email protected]> wrote: Hi Hao,
Looks good. > From: Kang Luwei <[email protected]> > > The Header Register set is always present for FPGA Management Engine (FME), > this patch implements init and uinit function for header sub feature and > introduce several read-only sysfs interfaces for the capability and status. > > Sysfs interfaces: > * /sys/class/fpga_region/<regionX>/<dfl-fme.x>/ports_num > Read-only. Number of ports implemented > > * /sys/class/fpga_region/<regionX>/<dfl-fme.x>/bitstream_id > Read-only. Blue Bitstream (static FPGA region) identifier number. It > contains > the detailed version and other information of this static FPGA region. > > * /sys/class/fpga_region/<regionX>/<dfl-fme.x>/bitstream_metadata > Read-only. Blue Bitstream (static FPGA region) meta data. It contains the > synthesis date, seed and other information of this static FPGA region. > > Signed-off-by: Tim Whisonant <[email protected]> > Signed-off-by: Enno Luebbers <[email protected]> > Signed-off-by: Shiva Rao <[email protected]> > Signed-off-by: Christopher Rauer <[email protected]> > Signed-off-by: Kang Luwei <[email protected]> > Signed-off-by: Xiao Guangrong <[email protected]> > Signed-off-by: Wu Hao <[email protected]> Acked-by: Alan Tull <[email protected]> Thanks, Alan
