On Fri 2018-03-09 10:26:11, Jose Abreu wrote: > Hi Niklas, > > On 08-03-2018 10:30, Niklas Cassel wrote: > > These wmb() memory barriers are performed after the last descriptor write, > > and they are followed by enable_dma_transmission()/set_tx_tail_ptr(), > > i.e. a writel() to MMIO register space. > > Since writel() itself performs the equivalent of a wmb() > > Sorry but I know at least two architectures which don't do a > wmb() upon an writel [1] [2]. This can be critical if if we are > accessing the device through some slow or filled bus which will > delay accesses to the device IO. Notice that writel and then > readl to the same address will force CPU to wait for writel > completion before readl, but in this case we are using DMA and > then writel so I think a wmb() before the writel is a safe measure.
This also matches documentation, as I tried to point out. -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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