Hi,
On 3/19/2018 11:21 PM, Evan Green wrote: > Hi Manu, > > On Fri, Mar 16, 2018 at 2:46 AM Manu Gautam <mgau...@codeaurora.org> wrote: [snip] >> index d1c6905..5d78d43 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-qmp.h >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h >> @@ -214,6 +214,8 @@ >> #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 >> #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 >> #define QSERDES_V3_RX_RX_TERM_BW 0x07c >> +#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc > I noticed you add this definition, but never use it. Are you missing a > QMP_PHY_INIT_CFG line for this register in qmp_v3_usb3_uniphy_rx_tbl[], or > is that register "don't care"? It looks important, and while its default > value out of reset might be valid, you never know what nutty value boot > firmware might set it to. > Yes POR value of this register is valid for this soc. QMP driver resets (asserts and de-asserts reset_control) in probe. So, that should ensure that PHY registers are indeed set to POR value. Left the definition there if different setting needed to be done for a different variant of h/w in future. -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
