On Wed, Apr 18, 2018 at 12:41:27PM +0800, Peter Xu wrote: > (PSI stands for: Page Selective Invalidations) > > Intel IOMMU has the caching mode to ease emulation of the device. > When that bit is set, we need to send PSIs even for newly mapped > pages. However current driver is not fully obey the rule. E.g., > iommu_map() API will only do the mapping but it never sent the PSIs > before. That can be problematic to emulated IOMMU devices since > they'll never be able to build up the shadow page tables if without > such information. This patchset tries to fix the problem. > > Patch 1 is a tracing enhancement that helped me to triage the problem. > It might even be useful in the future. > > Patch 2 generalized a helper to notify the MAP PSIs. > > Patch 3 fixes the real problem by making sure every domain mapping > will trigger the MAP PSI notifications. > > Without the patchset, nested device assignment (assign one device > firstly to L1 guest, then to L2 guest) won't work for QEMU. After > applying the patchset, it works. > > Please review. Thanks. > > Peter Xu (3): > intel-iommu: add some traces for PSIs > intel-iommu: generalize __mapping_notify_one() > intel-iommu: fix iotlb psi missing for mappings > > drivers/iommu/dmar.c | 3 ++ > drivers/iommu/intel-iommu.c | 68 > ++++++++++++++++++++++++++++++++------------- > 2 files changed, 52 insertions(+), 19 deletions(-)
Adding CC to Alexander Witte and Jintack. -- Peter Xu
