Commit-ID: ca2f6779608e364443cd82d31b1efd8b76f23bf6 Gitweb: https://git.kernel.org/tip/ca2f6779608e364443cd82d31b1efd8b76f23bf6 Author: Oskar Senft <o...@google.com> AuthorDate: Fri, 23 Mar 2018 09:11:30 -0400 Committer: Thomas Gleixner <t...@linutronix.de> CommitDate: Fri, 20 Apr 2018 12:41:17 +0200
perf/x86/intel/uncore: Fix SBOX support for Broadwell CPUs SBOX on some Broadwell CPUs is broken because it's enabled unconditionally despite the fact that there are no SBOXes available. Check the Power Control Unit CAPID4 register to determine the number of available SBOXes on the particular CPU before trying to enable them. If there are none, nullify the SBOX descriptor so it isn't tried to be initialized. Signed-off-by: Oskar Senft <o...@google.com> Signed-off-by: Thomas Gleixner <t...@linutronix.de> Tested-by: Mark van Dijk <m...@voidzero.net> Reviewed-by: Kan Liang <kan.li...@intel.com> Acked-by: Peter Zijlstra <pet...@infradead.org> Cc: a...@linux.intel.com Cc: pet...@infradead.org Cc: eran...@google.com Link: https://lkml.kernel.org/r/1521810690-2576-2-git-send-email-kan.li...@linux.intel.com --- arch/x86/events/intel/uncore_snbep.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index 5bbbbee11879..37e809d457c6 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -3060,6 +3060,8 @@ static struct event_constraint bdx_uncore_pcu_constraints[] = { void bdx_uncore_cpu_init(void) { + int pkg = topology_phys_to_logical_pkg(0); + if (bdx_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) bdx_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores; uncore_msr_uncores = bdx_msr_uncores; @@ -3067,7 +3069,16 @@ void bdx_uncore_cpu_init(void) /* BDX-DE doesn't have SBOX */ if (boot_cpu_data.x86_model == 86) uncore_msr_uncores[BDX_MSR_UNCORE_SBOX] = NULL; + /* Detect systems with no SBOXes */ + else if (uncore_extra_pci_dev[pkg].dev[HSWEP_PCI_PCU_3]) { + struct pci_dev *pdev; + u32 capid4; + pdev = uncore_extra_pci_dev[pkg].dev[HSWEP_PCI_PCU_3]; + pci_read_config_dword(pdev, 0x94, &capid4); + if (((capid4 >> 6) & 0x3) == 0) + bdx_msr_uncores[BDX_MSR_UNCORE_SBOX] = NULL; + } hswep_uncore_pcu.constraints = bdx_uncore_pcu_constraints; } @@ -3285,6 +3296,11 @@ static const struct pci_device_id bdx_uncore_pci_ids[] = { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f46), .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 2), }, + { /* PCU.3 (for Capability registers) */ + PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fc0), + .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, + HSWEP_PCI_PCU_3), + }, { /* end: all zeroes */ } };
