On Wed, Apr 25, 2018 at 3:37 AM, Maxime Ripard <maxime.rip...@bootlin.com> wrote: > On Tue, Apr 24, 2018 at 08:17:11PM +0800, Chen-Yu Tsai wrote: >> On Tue, Apr 24, 2018 at 8:13 PM, Maxime Ripard >> <maxime.rip...@bootlin.com> wrote: >> > On Tue, Apr 24, 2018 at 07:34:19PM +0800, Chen-Yu Tsai wrote: >> >> The Libre Computer Project ALL-H3-CC has three models, all using the >> >> same board design, but with different pin compatible SoCs and amount of >> >> DRAM. >> >> >> >> Currently only the H3 1GB DRAM variant is supported. To support the two >> >> other variants, first split the original device tree into a common board >> >> design part and an SoC specific part. >> >> >> >> The SoC part only defines which SoC is used and model name, and includes >> >> the SoC specific dtsi file and the common design dtsi file. >> >> >> >> Also fix up the SPDX identifier line to use the correct comment style, >> >> and place it on the first line. >> >> >> >> Signed-off-by: Chen-Yu Tsai <w...@csie.org> >> >> --- >> >> .../boot/dts/sun8i-h3-libretech-all-h3-cc.dts | 213 +----------------- >> >> ....dts => sunxi-hx-libretech-all-h3-cc.dtsi} | 11 +- >> > >> > I think I prefer the name of Neil's DTSI better, and since pretty much >> > the same patches (a couple of hours) before, we'll merge them (while >> > merging the rest of your patches, obviously). >> > >> > Does that work for you? >> >> I would like for the regulator voltage fix to be merged before the split. >> This will make it trivial to back port, instead of having to reverse the >> split, and maybe failing. > > Yes, I was just talking about replacing your two redundant patches, > but keeping the order you have.
That works for me. Might require a little fixing up. Let me know if you need help with that. ChenYu
