Hello Stefan,
On Tue, 22 May 2018 14:07:05 +0200
Stefan Agner <ste...@agner.ch> wrote:
> From: Lucas Stach <d...@lynxeye.de>
>
> This adds the devicetree binding for the Tegra 2 NAND flash
> controller.
>
> Signed-off-by: Lucas Stach <d...@lynxeye.de>
> Signed-off-by: Stefan Agner <ste...@agner.ch>
> ---
> .../bindings/mtd/nvidia,tegra20-nand.txt | 29 +++++++++++++++++++
> 1 file changed, 29 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
>
> diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
> b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
> new file mode 100644
> index 000000000000..522d442937a9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
> @@ -0,0 +1,29 @@
> +NVIDIA Tegra NAND Flash controller
> +
> +Required properties:
> +- compatible: Must be one of:
> + - "nvidia,tegra20-nand"
> +- reg: MMIO address range
> +- interrupts: interrupt output of the NFC controller
> +- clocks: Must contain an entry for each entry in clock-names.
> + See ../clocks/clock-bindings.txt for details.
> +- clock-names: Must include the following entries:
> + - nand
> +- resets: Must contain an entry for each entry in reset-names.
> + See ../reset/reset.txt for details.
> +- reset-names: Must include the following entries:
> + - nand
> +
> +Optional properties:
> +- nvidia,wp-gpios: GPIO used to disable write protection of the flash
> +
> + Example:
> + nand@70008000 {
> + compatible = "nvidia,tegra20-nand";
> + reg = <0x70008000 0x100>;
> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
> + clock-names = "nand";
> + resets = <&tegra_car 13>;
> + reset-names = "nand";
> + };
Can you represent the controller and NAND chip separately as
recommended here [1].
Thanks,
Boris
[1]https://elixir.bootlin.com/linux/v4.17-rc6/source/Documentation/devicetree/bindings/mtd/nand.txt#L56
