On 25/05/18 10:49, Julien Thierry wrote:
Provide a higher priority to be used for pseudo-NMIs. When such an interrupt is received, enter the NMI state and prevent other NMIs to be raised. When returning from a pseudo-NMI, skip preemption and tracing if the interrupted context has interrupts disabled. Signed-off-by: Julien Thierry <julien.thie...@arm.com> Cc: Russell King <li...@armlinux.org.uk> Cc: Catalin Marinas <catalin.mari...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Cc: Thomas Gleixner <t...@linutronix.de> Cc: Jason Cooper <ja...@lakedaemon.net> Cc: Marc Zyngier <marc.zyng...@arm.com> --- arch/arm/include/asm/arch_gicv3.h | 6 ++++++ arch/arm64/include/asm/arch_gicv3.h | 6 ++++++ arch/arm64/kernel/entry.S | 43 +++++++++++++++++++++++++++++++++++++ drivers/irqchip/irq-gic-v3.c | 41 +++++++++++++++++++++++++++++++++++ 4 files changed, 96 insertions(+)
[...]
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index b144f73..4be5996 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -371,6 +379,20 @@ static u64 gic_mpidr_to_affinity(unsigned long mpidr) return aff; }+static void do_handle_nmi(unsigned int hwirq, struct pt_regs *regs)+{ + struct pt_regs *old_regs = set_irq_regs(regs); + unsigned int irq; + + nmi_enter();
RAS/SEA also enters NMI state and things will break if asynchronous error occurs during a pseudo-NMI.
I'll have this fixed in the next version. -- Julien Thierry
