On Fri, 15 Jun 2018 15:55:41 +0200 Boris Brezillon <boris.brezil...@bootlin.com> wrote:
> On Fri, 15 Jun 2018 13:42:12 +0000 > Yogesh Narayan Gaur <yogeshnarayan.g...@nxp.com> wrote: > > > Hi Boris, > > > > I am still debugging the issue. > > With some analysis, able to check that proper values are not being written > > for QUADSPI_SFA2AD/ QUADSPI_SFB1AD/ QUADSPI_SFB2AD register. > > > > In current code, value of map_addr are being assigned to these register. > > map_addr = q->memmap_phy + > > 2 * q->devtype_data->ahb_buf_size; > > > > qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + (i * 4)); > > > > But instead of "q->devtype_data->ahb_buf_size" it should be flash size. > > No, because we're only using 2 * ->ahb_buf_size in the direct mapping > for each device, and we're modifying the mapping dynamically based on > the selected device. Maybe we got the logic wrong though. > > > For my case flash size is 0x4000000 and with this hard coded value I am > > able to perform Write and Erase operation. > > One more change, I have to do is adding the flash_size when writing the > > base_address in SFAR register for case when "mem->spi->chip_select == 1" > > qspi_writel(q, q->memmap_phy + 0x4000000, base + QUADSPI_SFAR); > > I don't want to expose the full device in the direct mapping yet > (that's part of the direct-mapping API I posted here [1]). What this > version of the driver does is, map only 2 time the ahb_size so that we > can bypass the internal cache of the QSPI engine. Oops, forgot to add the link. [1]http://lists.infradead.org/pipermail/linux-mtd/2018-June/081460.html
