On Fri, 15 Jun 2018 10:18:50 +0900, Masahiro Yamada
<[email protected]> wrote:
> According to the Denali User's Guide, this IP needs three clocks:
>
> - clk: controller core clock
>
> - clk_x: bus interface clock
>
> - ecc_clk: clock at which ECC circuitry is run
>
> Currently, denali_dt.c requires a single anonymous clock and its
> frequency. However, the driver needs to get the frequency of "clk_x"
> not "clk". This is confusing because people tend to assume the
> anonymous clock means the core clock. In fact, I got a report of
> SOCFPGA breakage because the timing parameters are calculated based
> on a wrong frequency.
>
> Instead of the cheesy implementation, the clocks in the real hardware
> should be represented in the driver and the DT-binding.
>
> However, adding new clocks would break the existing platforms. For the
> backward compatibility, the driver still accepts a single clock just as
> before. If clk_x is missing, clk_x_rate is set to a hardcoded value.
> This is fine for existing DT of Socionext UniPhier, and also fixes the
> issue of Altera (Intel) SOCFPGA because both platforms use 200 MHz for
> the bus interface clock.
>
> Fixes: 1bb88666775e ("mtd: nand: denali: handle timing parameters by
> setup_data_interface()")
> Cc: linux-stable <[email protected]> #4.14+
> Reported-by: Richard Weinberger <[email protected]>
> Signed-off-by: Masahiro Yamada <[email protected]>
> ---
>
Reviewed-by: Miquel Raynal <[email protected]>
Thanks,
Miquèl
