On Fri, Jun 15, 2018 at 10:18:50AM +0900, Masahiro Yamada wrote:
> According to the Denali User's Guide, this IP needs three clocks:
>
> - clk: controller core clock
>
> - clk_x: bus interface clock
>
> - ecc_clk: clock at which ECC circuitry is run
>
> Currently, denali_dt.c requires a single anonymous clock and its
> frequency. However, the driver needs to get the frequency of "clk_x"
> not "clk". This is confusing because people tend to assume the
> anonymous clock means the core clock. In fact, I got a report of
> SOCFPGA breakage because the timing parameters are calculated based
> on a wrong frequency.
>
> Instead of the cheesy implementation, the clocks in the real hardware
> should be represented in the driver and the DT-binding.
>
> However, adding new clocks would break the existing platforms. For the
> backward compatibility, the driver still accepts a single clock just as
> before. If clk_x is missing, clk_x_rate is set to a hardcoded value.
> This is fine for existing DT of Socionext UniPhier, and also fixes the
> issue of Altera (Intel) SOCFPGA because both platforms use 200 MHz for
> the bus interface clock.
>
> Fixes: 1bb88666775e ("mtd: nand: denali: handle timing parameters by
> setup_data_interface()")
> Cc: linux-stable <[email protected]> #4.14+
> Reported-by: Richard Weinberger <[email protected]>
> Signed-off-by: Masahiro Yamada <[email protected]>
> ---
>
> Changes in v3:
> - Change the patch order so that the bug-fix one comes the first
>
> Changes in v2:
> - Split patches into sensible chunks
>
> .../devicetree/bindings/mtd/denali-nand.txt | 5 +++
> drivers/mtd/nand/raw/denali_dt.c | 49
> ++++++++++++++++++++--
> 2 files changed, 50 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt
> b/Documentation/devicetree/bindings/mtd/denali-nand.txt
> index 0ee8edb..f33da87 100644
> --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/denali-nand.txt
> @@ -8,6 +8,9 @@ Required properties:
> - reg : should contain registers location and length for data and reg.
> - reg-names: Should contain the reg names "nand_data" and "denali_reg"
> - interrupts : The interrupt number.
> + - clocks: should contain phandle of the controller core clock, the bus
> + interface clock, and the ECC circuit clock.
> + - clock-names: should contain "nand", "nand_x", "ecc"
The subject says "add more clocks", but it doesn't look like any clocks
were supported before. Or documentation was missing?
Please split bindings to a separate patch.
Rob
