On Tue, Jun 26, 2018 at 12:22 AM <alanx.chi...@intel.com> wrote:
>
> From: "alanx.chiang" <alanx.chi...@intel.com>
Please fix your author name and send bindings to the DT list if you
want them reviewed.
>
> The AT24 series chips use 8-bit address by default. If some
> chips would like to support more than 8 bits, should add the compatible
> field for specfic chips in the driver.
>
> Provide a flexible way to determine the addressing bits through
> address-width in this patch.
>
> Signed-off-by: Alan Chiang <alanx.chi...@intel.com>
> Signed-off-by: Andy Yeh <andy....@intel.com>
>
> ---
> since v1:
> -- Remove the address-width field in the example.
>
> ---
> Documentation/devicetree/bindings/eeprom/at24.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/eeprom/at24.txt
> b/Documentation/devicetree/bindings/eeprom/at24.txt
> index 61d833a..9467482 100644
> --- a/Documentation/devicetree/bindings/eeprom/at24.txt
> +++ b/Documentation/devicetree/bindings/eeprom/at24.txt
> @@ -72,6 +72,8 @@ Optional properties:
>
> - wp-gpios: GPIO to which the write-protect pin of the chip is connected.
>
> + - address-width : number of address bits (one of 8, 16).
> +
> Example:
>
> eeprom@52 {
> --
> 2.7.4
>
