On Tue, Jul 10, 2018 at 11:34:45AM -0400, Alan Stern wrote:
> On Tue, 10 Jul 2018, Andrea Parri wrote:
>
> > > > ACQUIRE operations include LOCK operations and both smp_load_acquire()
> > > > and smp_cond_acquire() operations. [BTW, the latter was replaced by
> > > > smp_cond_load_acquire() in 1f03e8d2919270 ...]
> > > >
> > > > RELEASE operations include UNLOCK operations and smp_store_release()
> > > > operations. [...]
> > > >
> > > > [...] after an ACQUIRE on a given variable, all memory accesses
> > > > preceding any prior RELEASE on that same variable are guaranteed
> > > > to be visible.
> > >
> > > As far as I can see, these statements remain valid.
> >
> > Interesting; ;-) What does these statement tells you ;-) when applied
> > to a: and b: below?
> >
> > a: WRITE_ONCE(x, 1); // "preceding any prior RELEASE..."
> > smp_store_release(&s, 1);
> > smp_load_acquire(&s);
> > b: WRITE_ONCE(y, 1); // "after an ACQUIRE..."
>
> The first statement tells me that b: follows an ACQUIRE.
>
> The second tells me that a: precedes a RELEASE.
>
> And the third tells me that any READ_ONCE(x) statements coming po-after
> b: would see x = 1 or a later value of x. (Of course, they would have
> to see that anyway because of the cache coherency rules.)
Mmh, something like "visible from the same CPU of the ACQUIRE" probably
could have helped me to reach the same conclusion.
>
> More to the point, given:
>
> P0()
> {
> WRITE_ONCE(x, 1);
> a: smp_store_release(&s, 1);
> }
>
> P1()
> {
> b: r1 = smp_load_acquire(&s);
> r2 = READ_ONCE(x);
> }
>
> the third statement tells me that if r1 = 1 (that is, if a: is prior to
> b:) then r2 must be 1.
Indeed; the "prior" is ambiguous, but yes.
Andrea
>
> Alan
>
