2018-07-13 9:11 GMT+02:00 Linus Walleij <[email protected]>: > On Tue, Jul 10, 2018 at 9:53 AM Anson Huang <[email protected]> wrote: > >> GPIO registers could lose context on some i.MX SoCs, >> like on i.MX7D, when enter LPSR mode, the whole SoC >> will be powered off except LPSR domain, GPIO banks >> will lose context in this case, need to restore >> the context after resume from LPSR mode. >> >> This patch adds GPIO save/restore for those necessary >> registers, and put the save/restore operations in noirq >> suspend/resume phase, since GPIO is fundamental module >> which could be used by other peripherals' resume phase. >> >> Signed-off-by: Anson Huang <[email protected]> > > Hoping for some review on this before applying... > Fabio? Bartosz? > > Yours, > Linus Walleij
I'm not familiar with these SoCs but the code looks good and clean to me. Reviewed-by: Bartosz Golaszewski <[email protected]>
