Commit-ID: 6c0df8689494e1fefa685377676fa8192291a0eb Gitweb: https://git.kernel.org/tip/6c0df8689494e1fefa685377676fa8192291a0eb Author: Joerg Roedel <jroe...@suse.de> AuthorDate: Wed, 18 Jul 2018 11:40:58 +0200 Committer: Thomas Gleixner <t...@linutronix.de> CommitDate: Fri, 20 Jul 2018 01:11:42 +0200
x86/mm/pae: Populate valid user PGD entries Generic page-table code populates all non-leaf entries with _KERNPG_TABLE bits set. This is fine for all paging modes except PAE. In PAE mode only a subset of the bits is allowed to be set. Make sure to only set allowed bits by masking out the reserved bits. Signed-off-by: Joerg Roedel <jroe...@suse.de> Signed-off-by: Thomas Gleixner <t...@linutronix.de> Tested-by: Pavel Machek <pa...@ucw.cz> Cc: "H . Peter Anvin" <h...@zytor.com> Cc: linux...@kvack.org Cc: Linus Torvalds <torva...@linux-foundation.org> Cc: Andy Lutomirski <l...@kernel.org> Cc: Dave Hansen <dave.han...@intel.com> Cc: Josh Poimboeuf <jpoim...@redhat.com> Cc: Juergen Gross <jgr...@suse.com> Cc: Peter Zijlstra <pet...@infradead.org> Cc: Borislav Petkov <b...@alien8.de> Cc: Jiri Kosina <jkos...@suse.cz> Cc: Boris Ostrovsky <boris.ostrov...@oracle.com> Cc: Brian Gerst <brge...@gmail.com> Cc: David Laight <david.lai...@aculab.com> Cc: Denys Vlasenko <dvlas...@redhat.com> Cc: Eduardo Valentin <edu...@amazon.com> Cc: Greg KH <gre...@linuxfoundation.org> Cc: Will Deacon <will.dea...@arm.com> Cc: aligu...@amazon.com Cc: daniel.gr...@iaik.tugraz.at Cc: hu...@google.com Cc: keesc...@google.com Cc: Andrea Arcangeli <aarca...@redhat.com> Cc: Waiman Long <ll...@redhat.com> Cc: "David H . Gutteridge" <dhgutteri...@sympatico.ca> Cc: j...@8bytes.org Link: https://lkml.kernel.org/r/1531906876-13451-22-git-send-email-j...@8bytes.org --- arch/x86/include/asm/pgtable_types.h | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h index 99fff853c944..b64acb08a62b 100644 --- a/arch/x86/include/asm/pgtable_types.h +++ b/arch/x86/include/asm/pgtable_types.h @@ -50,6 +50,7 @@ #define _PAGE_GLOBAL (_AT(pteval_t, 1) << _PAGE_BIT_GLOBAL) #define _PAGE_SOFTW1 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW1) #define _PAGE_SOFTW2 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW2) +#define _PAGE_SOFTW3 (_AT(pteval_t, 1) << _PAGE_BIT_SOFTW3) #define _PAGE_PAT (_AT(pteval_t, 1) << _PAGE_BIT_PAT) #define _PAGE_PAT_LARGE (_AT(pteval_t, 1) << _PAGE_BIT_PAT_LARGE) #define _PAGE_SPECIAL (_AT(pteval_t, 1) << _PAGE_BIT_SPECIAL) @@ -266,14 +267,37 @@ typedef struct pgprot { pgprotval_t pgprot; } pgprot_t; typedef struct { pgdval_t pgd; } pgd_t; +#ifdef CONFIG_X86_PAE + +/* + * PHYSICAL_PAGE_MASK might be non-constant when SME is compiled in, so we can't + * use it here. + */ + +#define PGD_PAE_PAGE_MASK ((signed long)PAGE_MASK) +#define PGD_PAE_PHYS_MASK (((1ULL << __PHYSICAL_MASK_SHIFT)-1) & PGD_PAE_PAGE_MASK) + +/* + * PAE allows Base Address, P, PWT, PCD and AVL bits to be set in PGD entries. + * All other bits are Reserved MBZ + */ +#define PGD_ALLOWED_BITS (PGD_PAE_PHYS_MASK | _PAGE_PRESENT | \ + _PAGE_PWT | _PAGE_PCD | \ + _PAGE_SOFTW1 | _PAGE_SOFTW2 | _PAGE_SOFTW3) + +#else +/* No need to mask any bits for !PAE */ +#define PGD_ALLOWED_BITS (~0ULL) +#endif + static inline pgd_t native_make_pgd(pgdval_t val) { - return (pgd_t) { val }; + return (pgd_t) { val & PGD_ALLOWED_BITS }; } static inline pgdval_t native_pgd_val(pgd_t pgd) { - return pgd.pgd; + return pgd.pgd & PGD_ALLOWED_BITS; } static inline pgdval_t pgd_flags(pgd_t pgd)
