[PATCH 11/15] ARM: tegra: apalis-tk1: enable emmc ddr52 mode

[Marcel Ziswiler]

From: Marcel Ziswiler <marcel.ziswi...@toradex.com>

Add mmc-ddr-1_8v property enabling eMMC DDR52 mode.

root@apalis-tk1-mainline:~# cat /sys/kernel/debug/mmc2/ios
clock:          52000000 Hz
actual clock:   52000000 Hz
vdd:            21 (3.3 ~ 3.4 V)
bus mode:       2 (push-pull)
chip select:    0 (don't care)
power mode:     2 (on)
bus width:      3 (8 bits)
timing spec:    8 (mmc DDR52)
signal voltage: 1 (1.80 V)
driver type:    0 (driver type B)
root@apalis-tk1-mainline:~# hdparm -t /dev/mmcblk2

/dev/mmcblk2:
 Timing buffered disk reads: 256 MB in  3.02 seconds =  84.83 MB/sec

Signed-off-by: Marcel Ziswiler <marcel.ziswi...@toradex.com>

---

 arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 1 +
 arch/arm/boot/dts/tegra124-apalis.dtsi      | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi 
b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
index 6c255cb70339..13486fe407d2 100644
--- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
@@ -1919,6 +1919,7 @@
                non-removable;
                vmmc-supply = <&reg_module_3v3>; /* VCC */
                vqmmc-supply = <&reg_1v8_vddio>; /* VCCQ */
+               mmc-ddr-1_8v;
        };
 
        /* CPU DFLL clock */
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi 
b/arch/arm/boot/dts/tegra124-apalis.dtsi
index 72253d918ebd..77ca508d755e 100644
--- a/arch/arm/boot/dts/tegra124-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -1948,6 +1948,7 @@
                non-removable;
                vmmc-supply = <&reg_module_3v3>; /* VCC */
                vqmmc-supply = <&reg_1v8_vddio>; /* VCCQ */
+               mmc-ddr-1_8v;
        };
 
        /* CPU DFLL clock */
-- 
2.14.4