On Tue, 2018-08-07 at 13:18 +0200, Florian Eckert wrote: > Hello Andy > > I think this are the information you want to have. >
I was rather asking for something like TRM. By schematics, I meant a simplified GPIO buffers and pin control explained on hardware level. Below has nothing to do with either, unfortunately. > On 2018-08-04 20:22, Christian Lamparter wrote: > > As for the APUs. The vendor (PC Engines) happily provides > > PDFs and schematics for their boards: > > <https://www.pcengines.ch/pdf/apu1.pdf> > > <https://www.pcengines.ch/schema/apu1c.pdf> > > <https://www.pcengines.ch/pdf/apu2.pdf> > > <http://pcengines.ch/schema/apu2c.pdf> -- Andy Shevchenko <andriy.shevche...@linux.intel.com> Intel Finland Oy