On Mon, Sep 03, 2018 at 03:11:11PM +0530, [email protected] wrote: > From: Shubhrajyoti Datta <[email protected]> > > Disable interrupts while configuring the transfer and enable them back. > > We have below as the programming sequence > 1. start and slave address > 2. byte count and stop > > In some customer platform there was a lot of interrupts between 1 and 2 > and after slave address (around 7 clock cyles) if 2 is not executed > then the transaction is nacked. > > To fix this case make the 2 writes atomic. > > Signed-off-by: Shubhrajyoti Datta <[email protected]> > Signed-off-by: Michal Simek <[email protected]>
I assume simply changing the order of the register writes won't fix it? I also assume this is stable material?
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