On 2018/11/21 17:53, Peter Zijlstra wrote: > On Wed, Nov 21, 2018 at 09:19:36AM +0100, Peter Zijlstra wrote: >> On Wed, Nov 21, 2018 at 09:39:00AM +0800, Li, Aubrey wrote: >>>> Also; you were going to shop around with the other architectures to see >>>> what they want/need for this interface. I see nothing on that. >>>> >>> I'm open for your suggestion, :) >> >> Well, we have linux-arch and the various maintainers are also listed in >> MAINTAINERS. Go forth and ask.. > > Ok, so I googled a wee bit (you could have too). > > There's not that many architectures that build big hot chips > (powerpc,x86,arm64,s390) (mips, sparc64 and ia64 are pretty dead I > think, although the Fujitsu Sparc M10 X+/X SIMD looked like it could be > 'fun'). > > Of those, powerpc altivec doesn't seem to be very wide, but you'd have > to ask the power folks. Same for s390 z13. > > The Fujitsu/ARM64-SVE stuff looks like it can be big and hot. > > And RISC-V has was vector extention, but I don't think anybody is > actually building big hot versions of that just yet. > Thanks Peter. Add more maintainers here.
On some x86 architectures, the tasks using simd instruction(AVX512 particularly) need to be dealt with specially against the tasks not using simd instruction. I proposed an interface to expose such CPU specific information for the user space tools to apply different scheduling policies. The interface can be refined to be the format as /proc/<pid>/status. Not sure if it's useful to any other architectures. Welcome any comments. Thanks, -Aubrey
