Quoting A.s. Dong (2018-11-14 05:02:08) > i.MX7ULP Clock functions are under joint control of the System > Clock Generation (SCG) modules, Peripheral Clock Control (PCC) > modules, and Core Mode Controller (CMC)1 blocks > > The clocking scheme provides clear separation between M4 domain > and A7 domain. Except for a few clock sources shared between two > domains, such as the System Oscillator clock, the Slow IRC (SIRC), > and and the Fast IRC clock (FIRCLK), clock sources and clock > management are separated and contained within each domain. > > M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. > A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. > > This driver only adds clock support in A7 domain. > > Note that most clocks required to be operated when gated, e.g. pll, > pfd, pcc. And more special cases that scs/ddr/nic mux selecting > different clock source requires that clock to be enabled first, > then we need set CLK_OPS_PARENT_ENABLE flag for them properly. > > Cc: Stephen Boyd <[email protected]> > Cc: Michael Turquette <[email protected]> > Cc: Shawn Guo <[email protected]> > Cc: Anson Huang <[email protected]> > Cc: Bai Ping <[email protected]> > Signed-off-by: Dong Aisheng <[email protected]> > > ---
Applied to clk-next
