[PATCH v5 12/17] drm/sun4i: sun6i_mipi_dsi: Set proper vblk timing calculation

[Jagan Teki]

Unlike hblk, the vblk timings should follow an equation to compute
the desired value for lane 4 devices and rest of devices it would be 0.

BSP code from BPI-M64-bsp is computing vblk as for 4-lane devices
(from linux-sunxi
drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c)

tmp = (ht*dsi_pixel_bits[format]/8)*vt-(4+dsi_hblk+2);
dsi_vblk = (lane-tmp%lane);

So, update the vblk timing calculation accordingly.

Tested on 2-lane, 4-lane MIPI-DSI LCD panels.

Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
 drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 29 +++++++++++++++++++-------
 1 file changed, 22 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c 
b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
index d8947be92f9d..cbcef7bf7681 100644
--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
@@ -355,6 +355,27 @@ static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi,
                     SUN6I_DSI_INST_JUMP_CFG_NUM(1));
 };
 
+static u16 sun6i_dsi_get_timings_vblk(struct sun6i_dsi *dsi,
+                                     struct drm_display_mode *mode, u16 hblk)
+{
+       struct mipi_dsi_device *device = dsi->device;
+       unsigned int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8;
+       int tmp;
+
+       if (device->lanes != 4)
+               return 0;
+
+       /*
+        * The vertical blank is set using a blanking packet (4 bytes +
+        * payload + 2 bytes). Its minimal size is therefore 6 bytes
+        */
+#define VBLK_PACKET_OVERHEAD   6
+       tmp = (mode->htotal * Bpp) * mode->vtotal -
+             (hblk + VBLK_PACKET_OVERHEAD);
+
+       return (device->lanes - tmp % device->lanes);
+}
+
 static u16 sun6i_dsi_get_video_start_delay(struct sun6i_dsi *dsi,
                                           struct drm_display_mode *mode)
 {
@@ -503,13 +524,7 @@ static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi,
                   (mode->htotal - (mode->hsync_end - mode->hsync_start)) *
                   Bpp - HBLK_PACKET_OVERHEAD);
 
-       /*
-        * And I'm not entirely sure what vblk is about. The driver in
-        * Allwinner BSP is using a rather convoluted calculation
-        * there only for 4 lanes. However, using 0 (the !4 lanes
-        * case) even with a 4 lanes screen seems to work...
-        */
-       vblk = 0;
+       vblk = sun6i_dsi_get_timings_vblk(dsi, mode, hblk);
 
        /* How many bytes do we need to send all payloads? */
        bytes = max_t(size_t, max(max(hfp, hblk), max(hsa, hbp)), vblk);
-- 
2.18.0.321.gffc6fa0e3