On Fri, Nov 30, 2018 at 01:32:07PM +0530, Anup Patel wrote: > This patch provides irq_set_affinity() implementation for PLIC driver. > It also updates irq_enable() such that PLIC interrupts are only enabled > for one of CPUs specified in IRQ affinity mask.
But normally our affinity masks are that - masks of CPUs that can take it. It seems a bit odd to then just pick the first one, as this means with default all-CPU masks we'll have all interrupts handled by the first CPU only. > --- a/drivers/irqchip/irq-sifive-plic.c > +++ b/drivers/irqchip/irq-sifive-plic.c > @@ -106,14 +106,42 @@ static void plic_irq_toggle(const struct cpumask *mask, > int hwirq, int enable) > > static void plic_irq_enable(struct irq_data *d) > { > - plic_irq_toggle(irq_data_get_affinity_mask(d), d->hwirq, 1); > + unsigned int cpu = cpumask_any_and(irq_data_get_affinity_mask(d), > + cpu_online_mask); > + WARN_ON(cpu >= nr_cpu_ids); I think this should be WARN_ON_ONCE and actually return instead of then proceeding using the invalid cpu index. > +#ifdef CONFIG_SMP static int plic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, > + bool force) > +{ > + unsigned int cpu; > + > + if (!force) > + cpu = cpumask_any_and(mask_val, cpu_online_mask); > + else > + cpu = cpumask_first(mask_val); maybe swap the two branches around to avoid the inversion of the force flag?