Hi Miquel, > -----Original Message----- > From: Miquel Raynal [mailto:miquel.ray...@bootlin.com] > Sent: Monday, December 17, 2018 10:11 PM > To: Naga Sureshkumar Relli <nagas...@xilinx.com> > Cc: Boris Brezillon <boris.brezil...@bootlin.com>; r...@kernel.org; > rich...@nod.at; linux- > ker...@vger.kernel.org; marek.va...@gmail.com; linux-...@lists.infradead.org; > nagasures...@gmail.com; Michal Simek <mich...@xilinx.com>; > computersforpe...@gmail.com; dw...@infradead.org > Subject: Re: [LINUX PATCH v12 3/3] mtd: rawnand: arasan: Add support for > Arasan > NAND Flash Controller > > Hi Naga, > > [...] > > > Inserted biterror @ 48/7 > > Successfully corrected 25 bit errors per subpage Inserted biterror @ > > 50/7 ECC failure, invalid data despite read success > > root@xilinx-zc1751-dc2-2018_1:~# > > > > But even in this case also, driver is saying ECC failure but read success. > > That means controller is able to detect errors on read page up to 24 bit > > only. > > After that there is no way to say to the upper layers that the page is bad > > because of the > limitation in the controller. > > This is more than a "limitation", the design is broken. I am not sure how to > support such > controller, and I am not sure if we even want to.
The number of errors that are correctable is limited by a parameter 't'(total number of errors), If there is a condition that the number of errors greater than 't', then the controller won't be able to detect that. I guess this concept is same for other controllers as well. In Arasan it is limited to 24-bit. Even, in case of Hamming, it is 1-bit error correction and 2-bit error detection. What will happen if there are multiple errors(greater than 2-bit)? Thanks, Naga Sureshkumar Relli > > > Could you please suggest any alternative to report the errors in that case? > > Shall we support the controller without the hw ECC engine? Boris, any > thoughts? > > > Thanks, > Miquèl
