tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 8e143b90e4d45cca3dc53760d3cfab988bc74571
commit: 031337ace2d1c22a447da6390716fe92592cdd6e PCI: mediatek: Add loadable
kernel module support
date: 3 months ago
coccinelle warnings: (new ones prefixed by >>)
>> drivers/pci/controller/pcie-mediatek.c:720:13-16: WARNING: Suspicious code.
>> resource_size is maybe missing with mem
vim +720 drivers/pci/controller/pcie-mediatek.c
b099631d drivers/pci/host/pcie-mediatek.c Ryder Lee 2017-08-10 661
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 662
static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 663 {
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 664
struct mtk_pcie *pcie = port->pcie;
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 665
struct resource *mem = &pcie->mem;
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 666
const struct mtk_pcie_soc *soc = port->pcie->soc;
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 667
u32 val;
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 668
size_t size;
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 669
int err;
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 670
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 671
/* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 672
if (pcie->base) {
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 673
val = readl(pcie->base + PCIE_SYS_CFG_V2);
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 674
val |= PCIE_CSR_LTSSM_EN(port->slot) |
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 675
PCIE_CSR_ASPM_L1_EN(port->slot);
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 676
writel(val, pcie->base + PCIE_SYS_CFG_V2);
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 677
}
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 678
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 679
/* Assert all reset signals */
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 680
writel(0, port->base + PCIE_RST_CTRL);
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 681
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 682
/*
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 683
* Enable PCIe link down reset, if link status changed from link up to
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 684
* link down, this will reset MAC control registers and configuration
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 685
* space.
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 686
*/
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 687
writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 688
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 689
/* De-assert PHY, PE, PIPE, MAC and configuration reset */
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 690
val = readl(port->base + PCIE_RST_CTRL);
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 691
val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 692
PCIE_MAC_SRSTB | PCIE_CRSTB;
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 693
writel(val, port->base + PCIE_RST_CTRL);
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 694
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 695
/* Set up vendor ID and class code */
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 696
if (soc->need_fix_class_id) {
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 697
val = PCI_VENDOR_ID_MEDIATEK;
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 698
writew(val, port->base + PCIE_CONF_VEND_ID);
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 699
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 700
val = PCI_CLASS_BRIDGE_PCI;
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 701
writew(val, port->base + PCIE_CONF_CLASS_ID);
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 702
}
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 703
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 704
/* 100ms timeout value should be enough for Gen1/2 training */
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 705
err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 706
!!(val & PCIE_PORT_LINKUP_V2), 20,
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 707
100 * USEC_PER_MSEC);
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 708
if (err)
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 709
return -ETIMEDOUT;
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 710
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 711
/* Set INTx mask */
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 712
val = readl(port->base + PCIE_INT_MASK);
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 713
val &= ~INTX_MASK;
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 714
writel(val, port->base + PCIE_INT_MASK);
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 715
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 716
if (IS_ENABLED(CONFIG_PCI_MSI))
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 717
mtk_pcie_enable_msi(port);
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 718
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 719
/* Set AHB to PCIe translation windows */
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 @720
size = mem->end - mem->start;
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 721
val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size));
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 722
writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 723
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 724
val = upper_32_bits(mem->start);
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 725
writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 726
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 727
/* Set PCIe to AXI translation memory space.*/
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 728
val = fls(0xffffffff) | WIN_ENABLE;
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 729
writel(val, port->base + PCIE_AXI_WINDOW0);
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 730
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 731
return 0;
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 732 }
3828d60f drivers/pci/controller/pcie-mediatek.c Honghui Zhang 2018-10-15 733
:::::: The code at line 720 was first introduced by commit
:::::: 3828d60fd2ef99f97a677c1f95af2ab3e65e2576 PCI: mediatek: Fixup MSI
enablement logic by enabling MSI before clocks
:::::: TO: Honghui Zhang <[email protected]>
:::::: CC: Lorenzo Pieralisi <[email protected]>
---
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