> >
> > > > > +
> > > > > + msleep(st7701->sleep_delay);
> > > > > +
> > > > > + gpiod_set_value(st7701->reset, 0);
> > > > > +
> > > > > + gpiod_set_value(st7701->reset, 1);
> > > > > +
> > > > > + gpiod_set_value(st7701->reset, 0);
> > > > No timing constrains here? In prepare there are sleeps intermixed.
> > >
> > > Delay while doing unprare is not needed I suppose.
> >
> > If the purpose is alone to reset the display then a single write '0'
> > should do it I think
>
> I even tried this just set 0, since prepare is doing a sequence, it
> good behavior to do the reverse during handoff. ie reason I just
> initiated this sequence.
>
> > And there is a requirement that it must be low for a minimum of 10 us
> > which would be good to have here.
>
> Sorry, I didn't get this requirement what is this for?
The st7701 will ignore reset pulse shorter than 10 us - see Trw in
table 9 reset timing (page 54).
But as we just assert reset (set it to 0), this timing constraint can be
ignored.
> > I aslo found in chapter 9. (page 163 - second line) this statement:
> > "VDDA and VDDI must be powered down with minimum 120msec."
>
> Yes unprepare is doing the same, it exit from sleep out mode and wait
> for 120msec and do the reset.
>
> >
> > This is similar to the unprepare delay to be found in simple-panel.c
> > So an unprepare delay seems in order here.
>
> Look like simple-panel.c is doing delay after reset initiated and
> regulator disabled.
Sam
