On Fri, Jan 18, 2019 at 11:23:24AM -0500, Sasha Levin wrote: > From: Rui Zhao <ruiz...@microsoft.com> > > New driver supports DRAM error detection and correction on DMC520 > controller.
That's this thing, right? https://developer.arm.com/products/system-ip/memory-controllers/corelink-dmc-520 > Validated on actual hardware: Which is what exactly? This looks like a driver for the memory controller IP and that could get integrated in other platforms so I'd prefer if this driver was called <your_platform>_edac and the DMC520 was a generic piece of functionality like the FSL memory controller IP: mpc85xx_edac_mod-y := fsl_ddr_edac.o mpc85xx_edac.o obj-$(CONFIG_EDAC_MPC85XX) += mpc85xx_edac_mod.o layerscape_edac_mod-y := fsl_ddr_edac.o layerscape_edac.o obj-$(CONFIG_EDAC_LAYERSCAPE) += layerscape_edac_mod.o Thx. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.
