On Tue, Jan 22, 2019 at 11:56:32AM -0800, Sowjanya Komatineni wrote: > Below are the supported DMA types in Host Control1 Register > with Version 4 enable > b'00 - SDMA > b'01 - Not Used > b'10 - ADMA2 > b'11 - ADMA2 or ADMA3 > > ADMA3 uses Command Descriptor to issue an SD command. > A multi-block data transfer is performed by using a pair of CMD > descriptor and ADMA2 descriptor. > > ADMA3 performs multiple of multi-block data transfer by using > Integrated Descriptor which is more suitable for Command Queuing > to fetch both Command and Transfer descriptors. > > Host Capabilities register indiactes the supports of ADMA3 DMA. > > Signed-off-by: Sowjanya Komatineni <skomatin...@nvidia.com> > --- > [V10]: Changes are same as V9 except this series has SDHCI core changes > into seperate patch > > drivers/mmc/host/sdhci.c | 9 ++++++++- > drivers/mmc/host/sdhci.h | 2 ++ > 2 files changed, 10 insertions(+), 1 deletion(-)
Reviewed-by: Thierry Reding <tred...@nvidia.com>
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