On Mon, 21 Jan 2019 15:33:22 +0000, Julien Thierry <[email protected]> wrote: > > It is not supported to have some CPUs using GICv3 sysreg CPU interface > while some others do not. > > Once ICC_SRE_EL1.SRE is set on a CPU, the bit cannot be cleared. Since > matching this feature require setting ICC_SRE_EL1.SRE, it cannot be > turned off if found on a CPU. > > Set the feature as STRICT_BOOT, if boot CPU has it, all other CPUs are > required to have it. > > Signed-off-by: Julien Thierry <[email protected]> > Suggested-by: Daniel Thompson <[email protected]> > Reviewed-by: Suzuki K Poulose <[email protected]> > Reviewed-by: Mark Rutland <[email protected]> > Acked-by: Catalin Marinas <[email protected]> > Cc: Catalin Marinas <[email protected]> > Cc: Will Deacon <[email protected]> > Cc: Suzuki K Poulose <[email protected]> > Cc: Marc Zyngier <[email protected]>
Acked-by: Marc Zyngier <[email protected]> M. -- Jazz is not dead, it just smell funny.
