On Fri, 2018-12-14 at 14:01 -0800, Stephen Boyd wrote: > Quoting Weiyi Lu (2018-12-09 23:32:40) > > From: James Liao <[email protected]> > > > > Some modules may need to change its clock rate before turn on it. > > So changing PLL's rate when it is off should be allowed. > > This patch removes PLL enabled check before set rate, so that > > PLLs can set new frequency even if they are off. > > > > On MT8173 for example, ARMPLL's enable bit can be controlled by > > other HW. That means ARMPLL may be turned on even if we (CPU / SW) > > set ARMPLL's enable bit as 0. In this case, SW may want and can > > still change ARMPLL's rate by changing its pcw and postdiv settings. > > But without this patch, new pcw setting will not be applied because > > its enable bit is 0. > > > > (am from https://patchwork.kernel.org/patch/9411983/) > > Remove this. >
OK, I'll remove it. > > > > Signed-off-by: James Liao <[email protected]> > > Acked-by: Michael Turquette <[email protected]> > > Signed-off-by: Weiyi Lu <[email protected]>
