On 02/01/2019 09:07 AM, tudor.amba...@microchip.com wrote:
cut
>>> diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
cut
>>> +static int atmel_sam9x60_qspi_set_cfg(void __iomem *base,
>>> + const struct spi_mem_op *op,
>>> + struct atmel_qspi_cfg *cfg)
>>> +{
>>> + int ret = atmel_qspi_set_mode(cfg, op);
>>> +
>>> + if (ret)
>>> + return ret;
>>> +
>>> + ret = atmel_qspi_set_address_mode(cfg, op);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + cfg->ifr |= QSPI_IFR_INSTEN;
>>> + cfg->icr |= QSPI_ICR_INST(op->cmd.opcode);
>>> +
>>> + /* Set data enable */
>>> + if (op->data.nbytes)
>>> + cfg->ifr |= QSPI_IFR_DATAEN;
>>> +
>>> + if (!op->addr.nbytes) {
>>> + cfg->ifr |= QSPI_IFR_TFRTYP_TRSFR_REG;
>>> + if (op->data.dir == SPI_MEM_DATA_OUT)
>>> + cfg->ifr |= QSPI_IFR_APBTFRTYP_WRITE;
>>> + else
>>> + cfg->ifr |= QSPI_IFR_APBTFRTYP_READ;
>>> + } else {
>>> + cfg->ifr |= QSPI_IFR_TFRTYP_TRSFR_MEM;
>>
>> Can you try doing only regular transfers and let me know if it still
>> works. Support for mem transfers can then be added along with dirmap
>> support.
>
> should work. Will try and let you know.
you were right, it works. I will let mem transfer logic for dirmap support.
Cheers,
ta
