On Thu, Feb 07, 2019 at 09:18:16AM -0600, Bjorn Helgaas wrote: > On Fri, Dec 14, 2018 at 11:40:29AM +0800, honghui.zh...@mediatek.com wrote: > > From: Honghui Zhang <honghui.zh...@mediatek.com> > > > > The Class Code for subtractive decode PCI-to-PCI bridge is 060401h, > > change the class_mask values to make portdrv support this type bridge. > > I assume you have a Root Port or Switch Port that supports subtractive > decode? I'm trying to understand how such a device would work. > > Out of curiosity, can you show the "lspci -vv" output for the device > and the downstream devices of interest?
Actually, since subtractive decode has to do with how the bridge interacts with its *peers*, what would be interesting is the host bridge window information from ACPI _CRS or DT and the lspci info for everything under that host bridge. Assuming we're talking about a Root Port, I guess that would mean anything inside the host bridge windows but outside the positive decode windows (the normal PCI-PCI bridge apertures in the Root Ports) would be claimed by the subtractive decode Root Port? I guess you would want this because this path ultimately leads to an ISA or similar bus where you don't know what resources the device actually consumes? Bjorn
