On Thu, Feb 7, 2019 at 6:27 AM Lucas Stach <l.st...@pengutronix.de> wrote:
>
> Am Donnerstag, den 31.01.2019, 12:43 -0800 schrieb Andrey Smirnov:
> > Add nodes for two PCIe controllers found on i.MX8MQ.
> >
> > > Signed-off-by: Andrey Smirnov <andrew.smir...@gmail.com>
> > > Cc: Shawn Guo <shawn...@kernel.org>
> > > Cc: Fabio Estevam <fabio.este...@nxp.com>
> > > Cc: Chris Healy <cphe...@gmail.com>
> > > Cc: Lucas Stach <l.st...@pengutronix.de>
> > > Cc: Leonard Crestez <leonard.cres...@nxp.com>
> > > Cc: "A.s. Dong" <aisheng.d...@nxp.com>
> > > Cc: Richard Zhu <hongxing....@nxp.com>
> > Cc: linux-...@nxp.com
> > Cc: linux-arm-ker...@lists.infradead.org
> > Cc: linux-kernel@vger.kernel.org
> > ---
> > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 68 +++++++++++++++++++++++
> > 1 file changed, 68 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > index 89babc531380..d20e5c7e21a3 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > @@ -6,6 +6,7 @@
> >
> > #include <dt-bindings/clock/imx8mq-clock.h>
> > #include <dt-bindings/power/imx8mq-power.h>
> > +#include <dt-bindings/reset/imx8mq-reset.h>
> > #include <dt-bindings/gpio/gpio.h>
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > #include "imx8mq-pinfunc.h"
> > @@ -539,6 +540,73 @@
> > };
> >
> > };
> >
> > + pcie0: pcie@33800000 {
> > + compatible = "fsl,imx8mq-pcie";
> > + reg = <0x33800000 0x400000>,
> > + <0x1ff00000 0x80000>;
> > + reg-names = "dbi", "config";
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + device_type = "pci";
> > + bus-range = <0x00 0xff>;
> > + ranges = <0x81000000 0 0x00000000 0x1ff80000 0
> > 0x00010000 /* downstream I/O 64KB */
> > + 0x82000000 0 0x18000000 0x18000000 0
> > 0x07f00000>; /* non-prefetchable memory */
> > + num-lanes = <1>;
> > + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /*
> > eDMA */
>
> I don't think this IRQ is documented in any binding yet.
>
A leftover from vendor tree. Will drop in v2.
> > + interrupt-names = "msi";
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 0x7>;
> > + interrupt-map = <0 0 0 1 &gic GIC_SPI 125
> > IRQ_TYPE_LEVEL_HIGH>,
> > + <0 0 0 2 &gic GIC_SPI 124
> > IRQ_TYPE_LEVEL_HIGH>,
> > + <0 0 0 3 &gic GIC_SPI 123
> > IRQ_TYPE_LEVEL_HIGH>,
> > + <0 0 0 4 &gic GIC_SPI 122
> > IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> > + <&clk IMX8MQ_CLK_PCIE1_AUX>,
>
> This is not the PCIe bus clock. The bus clock is whatever drives the
> ref clock of the external bus. So on the i.MX8M-EVK this would be the
> fixed clock generated by U1302.
>
> The right thing to properly describe the HW is to extend the PCIe
> driver to look for the aux clock on i.MX8M, just like we do with the
> axi_inbound_clk on i.MX6SX.
>
OK, will update it in v2 and send a corresponding patch to PCI tree
once everything is agreed upon.
Thanks,
Andrey Smirnov
