On Wed, Feb 06, 2019 at 04:52:27PM +0100, Maxime Ripard wrote:
> Hi,
>
> On Wed, Feb 06, 2019 at 10:03:09AM +0000, Priit Laes wrote:
> > > > I'm concerned for other users of the PLL-PERIPH clock. AFAIK
> > > > all of them, except the HRTIMER, expect the clock rate to stay
> > > > the same and not change underneath them. And SATA expects it to
> > > > be at 600 MHz, as the datasheet says. And while it may not directly
> > > > apply to the LIME2, eMMC on newer SoCs / boards run at the slightly
> > > > reduced rate of 50 MHz just fine.
> > > >
> > > > In the commit in question, clocks without CLK_SET_RATE_PARENT
> > > > should be using the old code (now in the if conditional block),
> > > > i.e. the behavior should not have changed.
> > > >
> > > > I don't think this actually "fixes" whatever bug was introduced,
> > > > but only papers over the issue, and possible introduces further
> > > > issues for other users.
> > >
> > > You're right, I've overlooked that it was pll-periph being
> > > affected. I've dropped it for now.
> >
> > Any ideas what could be done. I currently have no time to debug it,
> > but it affects existing systems.
>
> I can't find what would change with that commit either if the flag
> isn't set, so looking at the register state before and after that
> commit would help I guess?
Register dump without the patch:
$ busybox devmem 0x01c20090
0x0250030E
pll-ddr-base 2 2 0 768000000 0 0 50000
pll-ddr-other 1 1 0 768000000 0 0 50000
mmc2 3 3 0 51200000 0 0 50000
Register dump with patch applied, booted from mmc0 and after mounting emmc:
$ busybox devmem 0x01c20090
0x8140020B
pll-periph-base 3 3 0 1200000000 0 0 50000
pll-periph 6 6 0 600000000 0 0 50000
mmc2 3 3 0 50000000 0 0 50000
>
> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
