On Wed, Feb 20, 2019 at 02:42:06PM +0200, Andy Shevchenko wrote:
> On Wed, Feb 20, 2019 at 12:24:40AM +0300, Yauhen Kharuzhy wrote:
> > Whiskey Cove Cherry Trail PMIC requires disabling OTG host mode before
> > of charger detection procedure. Do this by manipulationg of CHGRCTRL1
> > register.
> >
> > Source: APCI DSDT code of Lenovo Yoga Book YB1-X91L and open-sourced
> > Intel's drivers.
>
> Some minor comments below.
>
> Otherwise,
>
> Reviewed-by: Andy Shevchenko <[email protected]>
>
> > -#define CHT_WC_CHGRCTRL1 0x5e17
> > +#define CHT_WC_CHGRCTRL1 0x5e17
>
> Not related change?
just alignment, yes.
>
> > +#define CHT_WC_CHGRCTRL1_DBPEN_MASK BIT(7)
>
> Drop the _MASK, it's one bit anyway.
OK.
>
> > +#define CHT_WC_CHGRCTRL1_OTGMODE BIT(6)
> > +#define CHT_WC_CHGRCTRL1_FTEMP_EVENT BIT(5)
> > +#define CHT_WC_CHGRCTRL1_FUSB_INLMT_1500 BIT(4)
> > +#define CHT_WC_CHGRCTRL1_FUSB_INLMT_900 BIT(3)
> > +#define CHT_WC_CHGRCTRL1_FUSB_INLMT_500 BIT(2)
> > +#define CHT_WC_CHGRCTRL1_FUSB_INLMT_150 BIT(1)
> > +#define CHT_WC_CHGRCTRL1_FUSB_INLMT_100 BIT(0)
>
> I think better to keep ascending order.
OK.
>
> > +static void cht_wc_extcon_set_otgmode(struct cht_wc_extcon_data *ext,
> > + bool enable)
> > +{
> > + unsigned int chgrctrl1;
> > + int ret;
> > +
> > + ret = regmap_read(ext->regmap, CHT_WC_CHGRCTRL1, &chgrctrl1);
> > + if (ret) {
> > + dev_err(ext->dev, "Error reading CHGRCTRL1 reg: %d\n", ret);
> > + return;
> > + }
> > +
> > + if (enable)
> > + chgrctrl1 |= CHT_WC_CHGRCTRL1_OTGMODE;
> > + else
> > + chgrctrl1 &= ~(CHT_WC_CHGRCTRL1_OTGMODE);
>
> Redundant parens.
Hmm... Why I didn't use regmap_update_bits() here... I will simplify this
piece with it.
Thanks!
--
Yauhen Kharuzhy
