Quoting Katsuhiro Suzuki (2019-02-10 07:38:06) > Custom approximation of fractional-divider may not need parent clock > rate checking. For example Rockchip SoCs work fine using grand parent > clock rate even if target rate is greater than parent. > > This patch checks parent clock rate only if CLK_SET_RATE_PARENT flag > is set. > > For detailed example, clock tree of Rockchip I2S audio hardware. > - Clock rate of CPLL is 1.2GHz, GPLL is 491.52MHz. > - i2s1_div is integer divider can divide N (N is 1~128). > Input clock is CPLL or GPLL. Initial divider value is N = 1. > Ex) PLL = CPLL, N = 10, i2s1_div output rate is > CPLL / 10 = 1.2GHz / 10 = 120MHz > - i2s1_frac is fractional divider can divide input to x/y, x and > y are 16bit integer. > > CPLL --> | selector | ---> i2s1_div -+--> | selector | --> I2S1 MCLK
Applied to clk-next but I made the function into a macro because I don't see the benefit to exporting such a simple thing.
