On Wed, Feb 20, 2019 at 06:46:11PM +0900, Takao Indoh wrote: > On Thu, Feb 14, 2019 at 08:44:48PM +0000, Elliott, Robert (Persistent Memory) > wrote: > > * how does this interact with an iommu, if there is one? Must the > > address with bit 56 also be granted permission, or is that > > stripped off before any iommu comparisons? > > The latter. A bit 56 is cleared in Root Port before pass it to iommu.
What if the intendend destination is a peer and never hits the root port? Really, though, PCI device vendors need to just use the existing capability as intended and not have arch specific work-arounds. I'm sure nvme can't be the only device class you'd want this behavior.
