This patch adds the SAR ADC controller node. Signed-off-by: Neil Armstrong <narmstr...@baylibre.com> --- arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index 50e2cd36e08b..3bcddd412aa1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -278,6 +278,20 @@ clock-names = "xtal", "pclk", "baud"; status = "disabled"; }; + + saradc: adc@9000 { + compatible = "amlogic,meson-g12a-saradc", + "amlogic,meson-saradc"; + reg = <0x0 0x9000 0x0 0x48>; + #io-channel-cells = <1>; + interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>, + <&clkc_AO CLKID_AO_SAR_ADC>, + <&clkc_AO CLKID_AO_SAR_ADC_CLK>, + <&clkc_AO CLKID_AO_SAR_ADC_SEL>; + clock-names = "clkin", "core", "adc_clk", "adc_sel"; + status = "disabled"; + }; }; gic: interrupt-controller@ffc01000 { -- 2.20.1