Hi,
On Thu, Mar 07, 2019 at 03:41:01AM -0300, Alexandre Oliva wrote:
> On Feb 17, 2019, "Maciej W. Rozycki" <ma...@linux-mips.org> wrote:
>
> > Is there an MMIO completion barrier missing there somewhere by any chance
> > causing an IRQ that has been handled already to be redelivered because an
> > MMIO write meant to clear the IRQ at its origin at handler's completion
> > has not reached its destination before interrupts have been reenabled in
> > the issuing CPU? Just a thought.
>
> I've finally got a chance to bisect the IRQ14 (nobody cared) regression
> on my yeeloong. It took me to MIPS: Enforce strong ordering for MMIO
> accessors (commit 3d474dacae72ac0f28228b328cfa953b05484b7f).
This is interesting, thanks for the research, but I'm afraid it doesn't seem
to be the root cause.
While your patch seems to help also on Mini-PC (only briefly tested with
a dozen of reboots), there's still excessive amount of interrupts during
the boot - I'm getting something like 50000-70000, while with the old
IDE driver it's around 2500.
~ # cat /proc/irq/14/spurious
count 57805
unhandled 57799
last_unhandled 4294673092 ms
~ # cat /proc/interrupts
CPU0
2: 0 XT-PIC 2 cascade
3: 174 XT-PIC 3 ttyS0
5: 14653 XT-PIC 5 timer
11: 0 XT-PIC 11 ehci_hcd:usb1, ohci_hcd:usb2
14: 57805 XT-PIC 14 pata_amd
15: 0 XT-PIC 15 pata_amd
18: 0 MIPS 2 cascade
22: 0 MIPS 6 cascade
ERR: 0
Could you check your /proc/interrupts counters after the boot with
your change?
A.
