[PATCH V1 1/1] watchdog: f71808e_wdt: fix F81866 bit operation

[Ji-Ze Hong (Peter Hong)]

Fix error bit operation in watchdog_start()

Signed-off-by: Ji-Ze Hong (Peter Hong) <hpeter+linux_ker...@gmail.com>
---
 drivers/watchdog/f71808e_wdt.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/watchdog/f71808e_wdt.c b/drivers/watchdog/f71808e_wdt.c
index 9a1c761258ce..9129485732c7 100644
--- a/drivers/watchdog/f71808e_wdt.c
+++ b/drivers/watchdog/f71808e_wdt.c
@@ -387,18 +387,17 @@ static int watchdog_start(void)
 
        case f81866:
                /* Set pin 70 to WDTRST# */
-               superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL,
-                                 BIT(3) | BIT(0));
-               superio_set_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL,
-                               BIT(2));
+               superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL, 3);
+               superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL, 0);
+               superio_set_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL, 2);
+
                /*
                 * GPIO1 Control Register when 27h BIT3:2 = 01 & BIT0 = 0.
                 * The PIN 70(GPIO15/WDTRST) is controlled by 2Ch:
                 *     BIT5: 0 -> WDTRST#
                 *           1 -> GPIO15
                 */
-               superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_GPIO1,
-                                 BIT(5));
+               superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_GPIO1, 5);
                break;
 
        default:
-- 
2.7.4