On Wed, 2019-03-27 at 16:13 +0100, Neil Armstrong wrote:
> The vid_pll_div is a programmable fractional divider, but vendor gives a
> limited of known configuration value and it's corresponding fraction.
>
> Thus when at reset value (0) or unknown value, we cannot determine the
> result rate.
>
> The initial behaviour was to print a warning, but the warning triggers
> at each boot and when the clock tree is refreshed.
>
> This patch moves the print to debug and returns 0 instead of the
> parent rate.
>
> Fixes: 72dbb8c94d0d ("clk: meson: Add vid_pll divider driver")
> Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
> ---
> drivers/clk/meson/vid-pll-div.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Jerome Brunet <jbru...@baylibre.com>
