[+MarkR] On Wed, Mar 20, 2019 at 07:07:46PM -0700, Prasad Sodagudi wrote: > Preserves the bitfields of PMCR_EL0(AArch64) during PMU reset. > Reset routine should write a 1 to PMCR.C and PMCR.P fields only > to reset the counters. Other fields should not be changed > as they could be set before PMU initialization and their > value must be preserved even after reset. > > Signed-off-by: Prasad Sodagudi <psoda...@codeaurora.org> > --- > arch/arm64/kernel/perf_event.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c > index 4addb38..0c1afdd 100644 > --- a/arch/arm64/kernel/perf_event.c > +++ b/arch/arm64/kernel/perf_event.c > @@ -868,8 +868,8 @@ static void armv8pmu_reset(void *info) > * Initialize & Reset PMNC. Request overflow interrupt for > * 64 bit cycle counter but cheat in armv8pmu_write_counter(). > */ > - armv8pmu_pmcr_write(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C | > - ARMV8_PMU_PMCR_LC); > + armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_P | > + ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC);
No, I don't think this is right at all. Many of these bits are UNKNOWN out of reset, so you're throwing away our means of getting the PMU into a deterministic state. Who is setting which bits that you want to preserve and why? Will