Hi Chanwoo, On 4/30/19 6:47 AM, Chanwoo Choi wrote: > Hi, > > On 19. 4. 19. 오후 11:19, Lukasz Luba wrote: >> Define new IDs for clocks used by Dynamic Memory Controller in >> Exynos5422 SoC. >> >> Acked-by: Rob Herring <r...@kernel.org> >> Signed-off-by: Lukasz Luba <l.l...@partner.samsung.com> >> --- >> include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++- >> 1 file changed, 17 insertions(+), 1 deletion(-) >> >> diff --git a/include/dt-bindings/clock/exynos5420.h >> b/include/dt-bindings/clock/exynos5420.h >> index 355f469..abb1842 100644 >> --- a/include/dt-bindings/clock/exynos5420.h >> +++ b/include/dt-bindings/clock/exynos5420.h >> @@ -60,6 +60,7 @@ >> #define CLK_MAU_EPLL 159 >> #define CLK_SCLK_HSIC_12M 160 >> #define CLK_SCLK_MPHY_IXTAL24 161 >> +#define CLK_SCLK_BPLL 162 >> >> /* gate clocks */ >> #define CLK_UART0 257 >> @@ -195,6 +196,18 @@ >> #define CLK_ACLK432_CAM 518 >> #define CLK_ACLK_FL1550_CAM 519 >> #define CLK_ACLK550_CAM 520 >> +#define CLK_CLKM_PHY0 521 >> +#define CLK_CLKM_PHY1 522 >> +#define CLK_ACLK_PPMU_DREX0_0 523 >> +#define CLK_ACLK_PPMU_DREX0_1 524 >> +#define CLK_ACLK_PPMU_DREX1_0 525 >> +#define CLK_ACLK_PPMU_DREX1_1 526 >> +#define CLK_PCLK_PPMU_DREX0_0 527 >> +#define CLK_PCLK_PPMU_DREX0_1 528 >> +#define CLK_PCLK_PPMU_DREX1_0 529 >> +#define CLK_PCLK_PPMU_DREX1_1 530 >> +#define CLK_CDREX_PAUSE 531 >> +#define CLK_CDREX_TIMING_SET 532 > > I cannot find the usage code of both CLK_CDREX_PAUSE > and CLK_CDREX_TIMING_SET in these patchset. Thank you for this catch. I will remove them.
Regards, Lukasz > > Please remove them. > > (snip) >
