The current Multi MSI data programming fails if multiple end points
requesting MSI and multi MSI are connected with switch, i.e the current
multi MSI data being given is not considering the number of vectors
being requested in case of multi MSI.
Ex: Two EP's connected via switch, EP1 requesting single MSI first,
EP2 requesting Multi MSI of count four. The current code gives
MSI data 0x0 to EP1 and 0x1 to EP2, but EP2 can modify lower two bits
due to which EP2 also sends interrupt with MSI data 0x0 which results
in always invoking virq of EP1 due to which EP2 MSI interrupt never
gets handled.
Fix Multi MSI data programming with required alignment by
using number of vectors being requested.
Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe
Host Controller")
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gog...@xilinx.com>
---
V3:
- Added example description of the issue
---
drivers/pci/controller/pcie-xilinx-nwl.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c
b/drivers/pci/controller/pcie-xilinx-nwl.c
index 81538d7..8efcb8a 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -483,7 +483,16 @@ static int nwl_irq_domain_alloc(struct irq_domain *domain,
unsigned int virq,
int i;
mutex_lock(&msi->lock);
- bit = bitmap_find_next_zero_area(msi->bitmap, INT_PCI_MSI_NR, 0,
+
+ /*
+ * Multi MSI count is requested in power of two
+ * Check if multi msi is requested
+ */
+ if (nr_irqs % 2 == 0)
+ bit = bitmap_find_next_zero_area(msi->bitmap, INT_PCI_MSI_NR, 0,
+ nr_irqs, nr_irqs - 1);
+ else
+ bit = bitmap_find_next_zero_area(msi->bitmap, INT_PCI_MSI_NR, 0,
nr_irqs, 0);
if (bit >= INT_PCI_MSI_NR) {
mutex_unlock(&msi->lock);
--
2.7.4
