From: Kim Phillips <[email protected]> Allow users to symbolically specify L3 events for Family 17h processors using the existing AMD Uncore driver.
Signed-off-by: Kim Phillips <[email protected]> Cc: Janakarajan Natarajan <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Arnaldo Carvalho de Melo <[email protected]> Cc: Alexander Shishkin <[email protected]> Cc: Andi Kleen <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Borislav Petkov <[email protected]> Cc: "Martin Liška" <[email protected]> Cc: Thomas Richter <[email protected]> Cc: Hendrik Brueckner <[email protected]> Cc: [email protected] --- .../perf/pmu-events/arch/x86/amdfam17h/cache.json | 14 ++++++++++++++ tools/perf/pmu-events/jevents.c | 1 + 2 files changed, 15 insertions(+) diff --git a/tools/perf/pmu-events/arch/x86/amdfam17h/cache.json b/tools/perf/pmu-events/arch/x86/amdfam17h/cache.json index 5d9f9e172743..e38adf8927ae 100644 --- a/tools/perf/pmu-events/arch/x86/amdfam17h/cache.json +++ b/tools/perf/pmu-events/arch/x86/amdfam17h/cache.json @@ -311,5 +311,19 @@ "BriefDescription": "Total cycles spent with one or more fill requests in flight from L2.", "PublicDescription": "Total cycles spent with one or more fill requests in flight from L2.", "UMask": "0x1" + }, + { + "EventName": "l3_request_g1.caching_l3_cache_accesses", + "EventCode": "0x01", + "BriefDescription": "L3 cache accesses", + "UMask": "0x80", + "Unit": "L3PMC" + }, + { + "EventName": "l3_comb_clstr_state.request_miss", + "EventCode": "0x06", + "BriefDescription": "L3 cache misses", + "UMask": "0x01", + "Unit": "L3PMC" } ] diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index 58f77fd0f59f..fb2cc98c5b0e 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -236,6 +236,7 @@ static struct map { { "CPU-M-CF", "cpum_cf" }, { "CPU-M-SF", "cpum_sf" }, { "UPI LL", "uncore_upi" }, + { "L3PMC", "amd_l3" }, {} }; -- 2.21.0
